Targeting design, verification, and test challenges

IC AND SYSTEM designers continue to grapple with the challenges of ensuring high performance under tight power consumption constraints, escalating verification costs, and increasing test cost. The semiconductor industry is therefore seeking innovations to reduce design cost, design cycle time, and the cost associated with presilicon and postsilicon qualification. Solutions to these problems require rethinking about system design, design-space exploration, on-chip interconnects, presilicon validation, and manufacturing test. This general-interest issue of IEEE Design & Test covers many of the key themes that constitute the technical scope of the magazine. The issue covers a wide range of topics and highlights the diversity of the problems that must be tackled as we strive to meet demands for high-performance computing coupled with low power consumption, high reliability, and manageable cost. Our rethinking must start at a conceptual level, especially in terms of how we design the system architecture for achieving power/ performance efficiency. The implementation of such novel architectures also requires breakthroughs in design tools used for power estimation, verification, and test generation. The articles here include recent advances in design methods such as customization to achieve higher efficiency in terms of power and performance, accurate power estimation for multiprocessor system-on-chips (MPSoCs) based on networkon-chips (NoCs), and low-power and reliable onchip interconnects. This issue also includes articles on testbench acceleration to reduce the communication overhead associated with hardware accelerators, testing for small-delay defects to reduce test escapes, and synthesis of scan trees to minimize test time. This issue begins with ‘‘Customizable DomainSpecific Computing,’’ by Jason Cong et al. Parallel processing has often been advocated as a means to satisfy ever-growing demands for higher computing power. However, it is also recognized that highly parallel, general-purpose computing systems do not offer the best design solutions that can balance high performance with power consumption, heat dissipation, cost, and so forth. In this article, the authors show how we can learn from nature the human brain to design a customizable platform that can achieve efficiency through specialization. The key approach to cope with rapidly growing computational complexity is through specialization of customizable platforms for each application domain. The next article, ‘‘Exploring NoC-Based MPSoC Design Space with Power Estimation Models’’ by Luciano Ost et al., shows how we can accurately estimate power consumption early in the design flow for MPSoCs. The proposed power estimation tool lets designers carry out design-space exploration more effectively for complex systems. The article describes a simulation framework based on the abstract notion of ‘‘actors’’ to capture the dynamic behavior of a NoC. The third article, ‘‘Low-Power, Resilient Interconnection with Orthogonal Latin Squares’’ by Seung Eun Lee et al., highlights an important problem in on-chip interconnect design namely, that of ensuring that interconnects are reliable and that they consume low power. The authors show how the Orthogonal Latin Square Code (OLSC) can be used to protect interconnects against transient errors while simultaneously lowering energy consumption.